Hybrid arc flash mitigation system

ABSTRACT

A system including an arc flash sensor that detects an arc flash event and an arc flash mitigation device in communication with the sensor. The mitigation device includes a path of least resistance having a path input and a path output. The arc flash sensor is located downstream the output. The mitigation device includes an electro-mechanical switch between the input and the output and an actuator. The mitigation device also includes a bypass power switch device that includes a solid-state circuit interrupter and that conduct current between the input and the output in response to an open-circuit condition of the switch. A system controller is provided to generate a trigger to activate the actuator to generate the open-circuit condition of the switch, which causes the power switch device to interrupt a fault current associated with a fault event in response to detection of the arc flash event.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a continuation of, and claims priority under 35U.S.C. § 120 from, U.S. patent application Ser. No. 17/982,807, filedNov. 8, 2022, which is a continuation of, and claims priority from, U.S.patent application Ser. No. 17/070,464, filed Oct. 14, 2020, entitled“HYBRID ARC FLASH MITIGATION SYSTEM”, the contents of which areincorporated herein by reference.

BACKGROUND

The document describes systems and methods that are directed toelectrical power protection systems and methods and, more particularly,to a hybrid arc flash mitigation system to protect maintenance personneland electrical power equipment.

Arc flash events can cause significant damage to power distributionsystems such as switchgear and panelboards, as well as personnelinjuries. Circuit breakers and fuses can be used in switchgear toprovide protection when there is a short circuit fault. However, currentprotection systems have a relatively long response time to interruptpropagating hazardous currents associated with a short circuit fault andeliminate arc flash events, especially when it is a fault caused by lowlevel overcurrent.

Some prior art systems exist that create a bolted short circuitupstream, which transfers the fault current from the arc flash to theshort circuit path quickly. However, such systems may cause a lot ofthermal and mechanical stress (due to high fault current) to theelectrical system and its components.

Other protection systems can provide an arc flash elimination response(such as within 2 milliseconds (ms)) upon the detection of an arc flashevent by current and light sensors where the detection requires 2 ms.However, commutation of the current from the arc flash event downstreamis generally limited by the distance (i.e. impedance) between theprotection system and arc flash event location.

SUMMARY

Some embodiments of a system may include an arc flash sensor configuredto detect an arc flash event and an arc flash mitigation device incommunication with the arc flash sensor. The arc flash mitigation devicemay include a path of least resistance having a path input and a pathoutput. The arc flash sensor is located downstream of the path output.The arc flash mitigation device may include an actuator and anelectro-mechanical switch between the path input and the path output.The arc flash mitigation device may include a bypass power switch devicethat includes a solid-state circuit interrupter and that is configuredto conduct current between the path input and the path output inresponse to an open-circuit condition of the switch. A system controlleris provided to generate a trigger signal to activate the actuator togenerate the open-circuit condition of the electro-mechanical switch,which causes the bypass power switch device to interrupt a fault currentassociated with a fault event, in response to detection of the arc flashevent by the arc flash sensor.

In various embodiments, the arc flash sensor may include a plurality ofsensors that include at least one optical sensor and at least onecurrent sensor located downstream of the path output to detect the arcflash event. The system may further include a plurality of branchcircuits. Each branch circuit is monitored by at least one opticalsensor and at least one current sensor.

In various embodiments, the arc flash mitigation device may furtherinclude a current sensor coupled upstream the path output to detect ahigh-current fault event. The system controller is also configured togenerate a corresponding trigger signal to activate the actuator togenerate the open-circuit condition of the electro-mechanical switch tocause the bypass power switch device to interrupt a fault currentassociated with the high-current fault event in response to detection ofthe high-current fault event by the current sensor of the arc flashmitigation device.

In some embodiments, the system controller is configured to control thebypass power switch device for a normal mode of operation, an arc flashreduction mode or both. In the normal mode of operation, theelectro-mechanical switch is set in a closed-circuit condition by thesystem controller. In the arc flash reduction mode of operation, theelectro-mechanical switch is set to an open-circuit condition and thebypass power switch device is in an “ON” state.

In various embodiments, the bypass power switch device may include afirst transistor that includes an emitter; a second transistor thatincludes an emitter connected to the emitter of the first transistor;and a first voltage-dependent resistor having a first side connected toa collector of the first transistor and a second side connected to acollector of the second transistor. The collector of the firsttransistor may be connected to the path input. The first transistor andthe second transistor form a transistor pair.

In various embodiments, the bypass power switch device may furtherinclude a third transistor that includes an emitter; a fourth transistorthat includes an emitter connected to the emitter of the thirdtransistor; and a second voltage-dependent resistor having a first sideconnected to a collector of the third transistor and a second sideconnected to a collector of the fourth transistor. The collector of thethird transistor is connected to the collector of the second transistor,and the collector of the fourth transistor is connected to the path ofleast resistance between the output terminal of the switch and the pathoutput. The third transistor and the fourth transistor from a secondtransistor pair.

In various embodiments, the system may include a housing for housing theswitch, the path of least resistance, the bi-directional bypass powerswitch device and the system controller. The housing may have the formfactor of a molded case circuit breaker or an air circuit breaker.

In various embodiments, the arc flash mitigation device may furtherinclude an electro-mechanical switch device that includes theelectro-mechanical switch. The electro-mechanical switch device includesa vacuum interrupter. The actuator includes a Thompson coil orpiezo-electric actuator connected to the vacuum interrupter.

In various embodiments, the bypass power switch device may include acooling device.

In various embodiments, the system further includes a plurality ofbranch circuits downstream of the arc flash mitigation device. Each ofthe branch circuits includes an associated circuit breaker. Each of thecircuit breakers is configured to open upon detection of a rated faultcurrent. Each of the circuit breakers is configured to, after opening inresponse to detection of the rated fault current, send a reclose signalto the system controller. The system controller is further configuredto, upon receipt of a reclose signal from a circuit breaker: a)determine whether the arc flash event occurred downstream of the circuitbreaker that sent the reclose signal; and b) upon confirming that thearc flash event occurred downstream of the circuit breaker that sent thereclose signal, trigger the actuator that causes the electro-mechanicalswitch to reclose.

Some embodiments of a method may include protecting, by an arc flashmitigation device, at least one electrical circuit downstream orupstream the arc flash mitigation device. The arc flash mitigationdevice includes an actuator, electro-mechanical switch in a path ofleast resistance between a path input and the path output and bypasspower switch device that includes a solid-state circuit interruptercoupled to the path of least resistance. The method includes detecting,by an arc flash sensor, an arc flash event downstream of the pathoutput. The arc flash sensor is in communication with the arc flashmitigation device. The method includes triggering, by the arc flashmitigation device, the actuator to open the electro-mechanical switch inthe path of least resistance in response to detection of the arc flashevent by the arc flash sensor; and interrupting a fault currentrepresentative of the detected arc flash event by the bypass powerswitch device of the arc flash mitigation device.

In various embodiments, a system may include a plurality of branchcircuits where each of the branch circuits includes an associatedcircuit breaker and an arc flash mitigation device located upstream theplurality of branch circuits. The arc flash mitigation device mayinclude a path of least resistance having a path input and a path outputand an electro-mechanical switch between the path input and the pathoutput. The arc flash mitigation device may include a bypass powerswitch device that includes a solid-state circuit interrupter and thatis configured to conduct current between the path input and the pathoutput in response to an open-circuit condition of theelectro-mechanical switch and a current sensor configured to measure anamount of current at the path output to detect a high-current faultevent associated with a fault current flowing at a location in thesystem. The arc flash mitigation device may include a system controllerconfigured to generate a trigger signal to cause the solid-state circuitinterrupter to interrupt the fault current associated with thehigh-current fault event in response to detection of the high-currentfault event by the current sensor, where the high-current fault event isof a level that is at least a multiple of a rated current of one or moreof the circuit breakers of the branch circuits.

In various embodiments, the system may include an arc flash sensingsystem in communication with the system controller. The arc flashsensing system may include a plurality of arc flash sensors that includeat least one optical sensor and at least one current sensor locateddownstream of the path output to detect an arc flash event, where eachof the plurality of branch circuits is monitored by at least one opticalsensor and at least one current sensor.

In various embodiments, the system controller is also configured togenerate a corresponding trigger signal to activate the actuator togenerate the open-circuit condition of the electro-mechanical switch tocause the bypass power switch device to interrupt a fault currentassociated with the arc flash event in response to detection of the arcflash event by any one arc flash sensor of the arc flash sensing system.

In various embodiments, each of the circuit breakers is configured toopen upon detection of its rated fault current. Each of the circuitbreakers is configured to, after opening in response to detection of therated fault current, send a reclose signal to the system controller. Thesystem controller is further configured to, upon receipt of a reclosesignal from a circuit breaker: a) determine whether the location in thesystem was downstream of the circuit breaker that sent the reclosesignal; and b) upon confirming that the location in the system wasdownstream of the circuit breaker that sent the reclose signal, triggerthe actuator to cause the electro-mechanical switch to reclose.

In various embodiments, the system may include a main circuit breakerconnected to and upstream of the arc flash mitigation device andconfigured to provide electrical current to the plurality of branchcircuits when the electro-mechanical switch is in either of aclosed-circuit condition or the open-circuit condition.

In various embodiments, the bypass power switch device has a responsetime between 100 microseconds and 0.5 milliseconds to interrupt an arcflash event or a high-current fault event.

In various embodiments, the system may include an electrical circuitupstream the arc flash mitigation device, the electrical circuit isconfigured to conduct a maintenance procedure in at least one branchcircuit of the plurality of branch circuits. The arc flash mitigationdevice includes a selective maintenance mode that causes theopen-circuit condition of the electro-mechanical switch.

In various embodiments, the arc flash mitigation device furthercomprises an external control panel providing a user interface to selectthe maintenance mode.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a block diagram of a system employing a hybrid arcflash mitigation system.

FIG. 2A illustrates a schematic diagram of a hybrid arc flash mitigationsystem with an arc flash mitigation device in a first mode of operationaccording to some embodiments.

FIG. 2B illustrates a schematic diagram of the hybrid arc flashmitigation system with the arc flash mitigation device in a second modeof operation in according to some embodiments.

FIG. 3 illustrates a block diagram of a controller of the arc flashmitigation device of FIGS. 2A-2B interfaced with components of thehybrid arc flash mitigation system.

FIG. 4A illustrates a front perspective view of an arc flash mitigationdevice with a housing with a molded case circuit breaker (MCCB) formfactor.

FIG. 4B illustrates an end and side perspective view of the arc flashmitigation device of FIG. 4A with a portion of the housing removed.

FIG. 4C illustrates a side view of the arc flash mitigation device ofFIG. 4A with a portion of the housing removed.

FIG. 5 illustrates n example electrical switchgear configuration.

FIG. 6A illustrates a front perspective view of an arc flash mitigationdevice with a housing with an air circuit breaker (ACB) form factor.

FIG. 6B illustrates a front perspective view of the arc flash mitigationdevice of FIG. 6A with a portion of the housing removed.

FIG. 7 illustrates a front perspective view of an arc flash mitigationdevice with a housing with an air circuit breaker cassette form factor.

FIG. 8 depicts an example of internal hardware that may be included inany of the electronic components of the system, such as internalprocessing systems of computing devices, controllers and sensors.

FIG. 9 illustrates a schematic diagram a system with a hybrid arc flashmitigation system used for multiple branch circuits in electricswitchgear.

DETAILED DESCRIPTION

Specific example embodiments of the inventive subject matter now will bedescribed with reference to the accompanying drawings. This inventivesubject matter may, however, be embodied in many different forms andshould not be construed as limited to the embodiments set forth herein;rather, these embodiments are provided so that this disclosure will bethorough and complete, and will fully convey the scope of the inventivesubject matter to those skilled in the art. In the drawings, likenumbers refer to like items.

It will be understood that when an item is referred to as being“connected” or “coupled” to another item, it can be directly connectedor coupled to the other item or intervening items may be present. Forexample, devices are “electrically connected” if a conductive pathexists between the devices, even if the path includes one or moreintermediate components.

As used herein the term “and/or” includes any and all combinations ofone or more of the associated listed items.

The terminology used herein is for the purpose of describing particularembodiments only and is not intended to be limiting of the inventivesubject matter. As used herein, the singular forms “a”, “an” and “the”are intended to include the plural forms as well, unless expresslystated otherwise. It will be further understood that the terms“includes,” “comprises,” “including” and/or “comprising,” when used inthis specification, specify the presence of stated features, integers,steps, operations, items, and/or components, but do not preclude thepresence or addition of one or more other features, integers, steps,operations, items, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientificterms) used herein have the same meaning as commonly understood by oneof ordinary skill in the art to which this inventive subject matterbelongs. It will be further understood that terms, such as those definedin commonly used dictionaries, should be interpreted as having a meaningthat is consistent with their meaning in the context of thespecification and the relevant art and will not be interpreted in anidealized or overly formal sense unless expressly so defined herein.

FIG. 1 illustrates a block diagram of a system 10 employing a hybrid arcflash mitigation system 50. The hybrid arc flash mitigation system 50may include an arc flash mitigation device (AFMD) 100. Arc flashmitigation device 100 may include a housing 110 with a control panel120. Control panel 120 may include a display panel 125 and an indicator130. Indicator 130 may include a light indicator including a lightemitting diode (LED), another type of light, or some other type ofindicator device. By way of non-limiting example, activating arc flashmitigation device 100 may cause the light indicator 130 to illuminate.The light indicator 130 may allow personnel 20 to determine that arcflash mitigation device 100 is armed or “ON” before starting amaintenance procedure.

Display panel 125 may include a liquid crystal display (LCD) or LEDdisplay. Display panel 125 may include a touch sensitive user interfacefor receiving user input. Control panel 120 may include control buttons132 and 134 such as for arming, disarming and/or resetting,respectively, arc flash mitigation device 100. One or more components ofarc flash mitigation device 100 may include a solid-state design. Thedetails of arc flash mitigation device 100 will be described in moredetail in relation to FIGS. 2A-2B and 3 .

Housing 110 houses protection electronic circuitry 105 of arc flashmitigation device 100, denoted in FIG. 1 as a dashed box. Protectionelectronic circuitry 105 may include a path of least resistance 107. InFIG. 1 , path of least resistance 107 includes an electro-mechanicalswitch SW1, which will be described in more detail in relation to FIGS.2A-2B. In FIG. 1 , switch SW1 is “OPEN” forming an open-circuit withinprotection electronic circuitry 105 along the path of least resistance107 when arc flash mitigation device 100 is activated or armed.

The system 10 may include an electrical circuit 35 that from time totime requires maintenance by personnel 20. Electrical circuit 35 may bea sub-component of an electrical power machine or an element ofelectrical distribution equipment. For example, the machine or equipmentmay include switchgear, a switchboard or a panelboard. Electricalcircuit 35 may include an electrical power circuit. Personnel 20 may berequired to connect an electrical circuit 25, such as an electricaltester or other device electrically to the electrical circuit 35 toperform a test or the other maintenance action. The electrical circuit25 may generate an electrical current representative of a test signal.The electrical circuit 25 may expect a response or return signal fromelectrical circuit 35. As will be described in more detail below, arcflash mitigation device 100 when armed is configured to protectpersonnel 20 by interrupting a fault current of a fault event.

Hybrid arc flash mitigation system 50 may include an arc flash sensorsystem (AFSS) 150 that is configured to sense an arc flash eventdownstream of the arc flash mitigation device 100 such as a flash oflight 15 or a current representative of an arc flash. In response todetecting the flash of light 15 from the arc flash, arc flash sensorsystem 150 provides a fault signal to arc flash mitigation device 100.The arc flash sensor system 150 may include an arc flash sensor. Thedetection of a flash of light and generation of the fault signal willoccur more quickly than a standard current sensing branch breaker mayact, and even more quickly than the system's main breaker may act. Arcflash mitigation device 100 also may include a current sensor, as willbe described in more detail in relation to FIGS. 2A-2B and 3 , toprovide a (second) fault signal to arc flash mitigation device 100 inresponse to detecting a very high level of fault current in the system.

Housing 110 may include a form factor substantially similar to that of acircuit breaker, as will be described later in relation to FIGS. 4A-4C.Housing 110 may have a molded case. Packaging for arc flash mitigationdevice 100 in such a housing may find particularly advantageousapplication in providing arc fault mitigation in an electricalpanelboard or other equipment at a location suited for installation of astandard form factor breaker. However, it should be understood, that theembodiments are not limited to such a form factor.

FIG. 2A illustrates a schematic diagram of hybrid arc flash mitigationsystem 50 with arc flash mitigation device 100 in a first mode ofoperation according to some embodiments. The first mode corresponds to adisarmed mode or normal mode of operation of protection electroniccircuitry 105 with electro-mechanical switch SW1 “CLOSED” or in aclosed-circuit condition. Switch SW1 is configured to have a loweron-resistance along the path of least resistance 107. FIG. 2Billustrates a schematic diagram of hybrid arc flash mitigation system 50with arc flash mitigation device 100 in a second mode of operation inaccording to some embodiments. The second mode corresponds to an armedmode of protection electronic circuitry 105 with electro-mechanicalswitch SW1 “OPEN” or in an open-circuit condition, such that anopen-circuit condition is formed along the path of least resistance 107;and an alternate bi-directional bypass path through an electronicbi-directional bypass power switch device 201 to vacuum interrupter 310of electro-mechanical switching device 210 is created. Theelectro-mechanical switching device 210 is described in more detail inrelation to FIG. 3 . The path of least resistance 107 when switch SW1 is“CLOSED” may be bi-directional.

FIGS. 2A and 2B show the same arc flash mitigation device 100 structure,but in different modes of operation.

Bi-directional bypass power switch device 201 may include a solid-statecircuit interrupter to interrupt the fault current of the fault event.In particular, bypass power switch device 201 is electrically connectedto a system controller 250. Arc flash mitigation device 100 may beelectrically connected to arc flash sensor system 150. Specifically, thearc flash sensor of the arc flash sensor system 150 may include a visionsystem 280 (FIGS. 2A and 2B) with one or more optical sensors 981 (FIG.9 ), such as cameras or other image capture devices that can detect aflash of light 15. Arc flash sensor system 150 may include a flashsensor controller 284 that is separate from the controller 250 of arcflash mitigation device 100. The arc flash sensor of the arc flashsensor system 150 may include current sensors 982 (FIG. 9 ) of anArcflash Reduction Maintenance System™ (ARMS) by Eaton® Corporation oranother suitable current sensor system. In operation, an optical sensor981 of the arc flash sensor system 150 is configured to visually detectillumination of the flash of light 15. In response to detection of theflash of light 15, arc flash sensor system 150 may communicate a (faultsignal on communication line 155 to arc flash mitigation device 100. Thefault signal on communication line 155 may denote detection of an arcflash event. The flash sensor controller 284 may include an arcdetection relay 286 to send a subsequent signal to arc flash mitigationdevice 100 when optical sensor 981 (FIG. 9 ) senses a flash of light 15.Optionally, flash sensor controller 284 may use image processing,feature extraction or other machine learning algorithms to detect froman image a level of illumination representative of an arc flash event.In other embodiments, the optical sensor may detect or sense a level ofillumination. Arc flash sensor system 150 will be described in moredetail in relation to FIG. 9 .

Upon receiving a fault signal on communication line 155 from arc flashsensor system 150, controller 250 may send a trigger signal on triggerconductor 255 to an ultra-fast actuator 240 in response to an arc flashevent to open switch SW1. Ultra-fast actuator 240 will be ultra-fast inthat is capable of acting more quickly than branch breakers and/or amain breaker of the system. For example, the switch SW1 may includecontacts 313 and 323 (FIG. 3 ) of the electro-mechanical switchingdevice 210 that will be forced to separate (open) to at least 1millimeter (mm) distance within a few hundred microseconds (μs) drivenby the ultra-fast actuator 240, as will be described in more detail inrelation to FIG. 3 . The controller 250 also may be responsive to aseparate (first) fault signal from a current sensor 270 in-line of thepath of least resistance 107, or to a signal from a current sensor thatis connected to the arc flash sensing system 150 as described below.Controller 250 may send a trigger signal on trigger conductor 255 toactuator 240 in response to a high-current fault event detected bysensor 270. Hybrid arc flash mitigation system 50 includes an arc flashsensor that may include both an optical sensor and a current sensor todetect an arc flash event or high-current fault event, both of which maybe referred to as a “fault event.” The current sensor 270 may detectcurrent along the path of least resistance 107 or upstream of the arcflash mitigation system 50 and be triggered by a current level thatexceeds a threshold that corresponds to a high risk of an arc flashevent 15. Hybrid arc flash mitigation system 50, using signals fromeither of the optical sensors or the current sensors, may take about 2ms to detect and confirm via controller 250 the fault event, which willsend a trigger signal to the electro-mechanical switching device 210.Within approximately 2.5 ms, the fault current of the fault event can beinterrupted by hybrid arc flash mitigation system 50.

Current sensor 270 may detect a high-current fault (i.e., a fault eventin which the current exceeds a threshold that is at least a multiple ofa rated current of a downstream branch breaker and/or an upstream mainbreaker). Upon detection of a high-current fault event, the currentsensor 270 may send a signal that may also cause controller 250 to senda trigger signal propagated along trigger conductor 255 to activate theactuator 240. The high-current fault event, which may be 2× the ratedcurrent of a branch breaker, 2.5× the rated current of a branch breaker,6× the rated current of a branch breaker, or another multiple of anotherbreaker's rated current, will represent a high degree of risk of an arcfault. In addition, hybrid arc flash mitigation system 50 can be usedrepetitively.

After bypass power switch device 201 interrupts the fault event, hybridarc flash mitigation system 50 can communicate with the individualbranch to determine which branch of a power system the fault resides onby getting current measurement levels, tripping that breaker (orreceiving a signal from that breaker confirming it opens), and thenrestoring power through a power electronic device, as will be describedin more detail in relation to FIG. 9 .

Circuit breakers, sometimes referred to as circuit interrupters, includeelectrical contacts that connect to each other to pass current from asource to a load. The contacts may be separated by force in order tointerrupt the delivery of current, either in response to a command or toprotect electrical systems from electrical fault conditions such ascurrent overloads, short circuits, and high or low voltage conditions.In some embodiments, electro-mechanical switching device 210 may becoupled to the ultra-fast actuator 240 to create the force to separatethe contacts. An ultra-fast actuator 240 will be configured to open theswitch SW1 to achieve at least 1 millimeter (mm) contact gap within aresponse time of approximately 0.5 ms. Electro-mechanical switchingdevice 210 will be described in more detail in relation to FIG. 3 .

The term “node” as used herein may refer to a connection or a connectionlocation. As a point of reference, assume that node N01 on the path ofleast resistance 107 is an input node configured to receive anelectrical current on line L01 from an external electrical circuit 25,for example. The path of least resistance 107 may begin with node N01.Hence, node N01 may also be referred to as an input or path input. Theelectrical current at node N01 may propagate along line L02 and toswitch SW1. As the electrical current propagates through switch SW1, theelectrical current propagates along line L04 to node N20, for example.Switch SW1 includes an output terminal T01.

In the closed-circuit condition, representative switching arm A1 ofswitch SW1 is oriented so that an electrical current flowing on line L02passes through switch SW1 to line L04 also part of the path of leastresistance 107. The switch arm A1 is for illustrative purposes and notmeant to limit the configuration or operation of the switch SW1 in anyway. The path of least resistance 107 continues from node N20 to theoutput at node N30. Node N20 may provide a bypass path from node N01 onan input side of switch SW1 to the second output side of switch SW1in-line with node N20 on the path of least resistance 107.

The bypass power switch device 201 is a bi-directional bypass switchcircuit, denoted in a dashed box positioned below the path of leastresistance 107 and is configured to interrupt the fault current of thefault event. From node N01, the electrical current may propagate in thedirection of arrow 109A to bi-directional bypass switch circuit (i.e.,power switch device 201) along line L12 to node N03, such as when switchSW1 is “OPEN.”

The electrical current on line L12 may propagate in the direction ofarrow 109B to a first insulated gate bipolar transistor (IGBT)transistor 203 connected to a second IGBT transistor 205. IGBTs 203 and205 may be a pair of IGBTs such that the emitters of IGBTs 203 and 205are tied together. A first side of voltage-dependent resistor (VDR) orvaristor 213 and a first side of the IGBTs 203 and 205 are connected tonode N03. Specifically, the collector of IGBT 203 is connected to thefirst side of varistor 213. A second side of the IGBTs 203 and 205 isconnected to node N13 where a second side of varistor 213 is alsoconnected to node N13. Specifically, the collector of IGBT 205 isconnected to node N13. Node N13 is adjacent to node N16.

A third IGBT transistor 207 is connected to a fourth IGBT transistor209. IGBTs 207 and 209 may be a pair of IGBTs such that the emitters ofIGBTs 207 and 209 are tied together. A first side of voltage-dependentresistor (VDR) or varistor 215 and a first side of the IGBTs 207 and 209are connected to node N16. Specifically, the collector of IGBT 207 isconnected to the first side of varistor 215. A second side of the IGBTs207 and 209 is connected to node N18 where a second side of varistor 215is also connected to node N18. Specifically, the collector of IGBT 209is connected to node N18. Line L16 extends from node N18 to node N20 onthe path of least resistance 107 where node N20 is between the outputterminal T01 of switch SW1 and the path output (i.e., node N30), by wayof example. In the bypass power switch device 201 current can flow inthe direction of arrow 109C to node N20, such as when theelectro-mechanical switching device 210 is in an open condition.Although this description indicates that IGBTs will be used, in someembodiments other types of transistors may be used.

The bypass power switch device 201 can have two pairs of thetransistors, as illustrated in FIGS. 2A-2B. The bypass power switchdevice 201 may be configured with multiple pairs of transistors.

The IGBTs may be substituted with metal oxide silicone field effecttransistors (MOSFETs) or junction gate field effect transistors (JFET)or other semiconductor power electronic switching devices.

Current sensor 270 is downstream of switch SW1 in proximity to the nodeN30, sometimes referred to as the “output” or “path output.” Currentsensor 270 is configured to sense an amount of current on line L25.Current sensor 270 is in electronic communication with or electricallyconnected to controller 250 and may deliver a sensed current signal online 275 representative of a measure of electric current on line L25. Inother variations, the sensed current signal may produce a (first) faultdetection signal, which is communicated to the controller 250 when thesensed signal is at a predefined threshold that would cause injury topersonnel 20.

FIG. 3 illustrates a block diagram of a controller 250 of the arc flashmitigation device 100 of FIGS. 2A-2B interfaced with components of thedevice. Controller 250 is in electrical communication or connected withcontrol panel 120 to receive a first control signal on line 303. Forexample, personnel 20 may place arc flash mitigation device 100 in thenormal mode of operation in response to the first control signalgenerated by control panel 120. The normal mode of operation correspondsto the arc flash reduction maintenance mode being “OFF,” thus thecontroller 250 sets the switch SW1 to the closed-circuit condition.Controller 250 may be responsive to control buttons 132 and 134 such asfor arming and disarming, respectively, arc flash mitigation device 100.Arming the arc flash mitigation device 100 turns “ON” the arc flashreduction maintenance mode such that the switch SW1 is set to theopen-circuit condition.

Control panel 120 may generate the first control signal on line 303 tocause controller 250 to control the operational mode of device 100. Theline 303 may be connected to a control panel input or port of controller250. The signals received on the control panel input or port ofcontroller 250 controls the operation (arm process or disarm process) ofthe controller. Thus, the control panel may generate disarming controlsignal to disarm device 100 and an arming control signal to arm arcflash mitigation device 100. Controller 250 may be powered althoughdevice 100 is disarmed, as the disarmed mode generally changes thecondition of the switch SW1.

Specifically, for the normal mode of operation, the controller 250 maycause switch SW1 to transition to the closed-circuit condition as shownin FIG. 2A, represented as switch arm A1 connected to the outputterminal T01. Arrow 101 represents the normal current flow through thearc flash mitigation device 100 when switch SW1 is set to theclosed-circuit condition of the normal mode of operation. Accordingly,the path of least resistance 107 extends from node N01 to node N30without an open-circuit condition. Controller 250 may send controlsignals in some embodiments on at least one control line 309 to controlbypass power switch device 201 to switch to “OFF.” Furthermore,controller 250 may control active cooling device 345 of the bypass powerswitch device 201, if present. Control panel 120 may generate a secondcontrol signal on line 303 to cause controller 250 to control theoperational mode of device 100 to cause switch SW1 to “OPEN,” as bestseen in FIG. 2B, such that device 100 becomes armed. In other words, theswitch SW1 has an open-circuit condition represented as switch arm A1being lifted in a direction away from terminal T01.

Controller 250 may include at least one processor 355. Hardware detailsof controller 250 will be described in more detail in relation to FIG. 8. Controller 250 may also include hardware, software and/or firmware forperforming an arming process 360 and a disarming process 365. Thedisarming process 365 configures arc flash mitigation device 100 tooperate according to the normal mode of operation, as shown in FIG. 2Aand described above. For example, the disarming process 365 may causecontroller 250 to control switch SW1 to “CLOSE” or transition to aclosed-circuit condition in response to the control signal on line 303.

The disarming process may cause the arc flash reduction maintenance modeto be switched “OFF.” Additionally, switch SW1 may be set to be in a“CLOSE” position and the bypass power switch device 201 can be either inan “OFF” state or in an “ON” state. In various embodiments, the bypasspower switch device 201 may remain in an “ON” state when the arc flashreduction maintenance mode is “OFF.”

Arming process 360 may cause controller 250 to control switch SW1 to“OPEN” or transition to an open-circuit condition relative to the pathof least resistance 107 in response to a second control signal on line303. Switch SW1, when “OPEN” relative to the path of least resistance107, is represented as switch arm A1 lifted away from terminal T01.Switch SW1 has a low on-resistance. Arming process 360 may also causecontroller 250 to set or reset ultra-fast actuator 240 and may cause thearc flash reduction maintenance mode to be turned “ON.” In someembodiments, the arming process 360 may engage switch SW1 which may bepart of a vacuum interrupter 310, in some embodiments, to cause contacts313 and 323 to separate from each other or “OPEN” the switch SW1. Thevacuum interrupter 310 may include a vacuum chamber 315, such as in aceramic bottle, where an arc is drawn by separating contacts 313 and323. When actuator 240 is reset, linkage 330 and actuator 240 areconfigured to maintain contacts 313 and 323 electrically open. Device100 is also capable of reuse under control of controller 250 after anarc flash event is detected and cleared.

Controller 250 may also include a trigger generator 370, a first faultdetector 372, and a second fault detector (comparer) 375, which mayinclude hardware, software and/or firmware. While arc flash mitigationdevice 100 is armed, first fault detector 372 may determine that a faultsignal on line 155 has been received from arc flash sensor system 150.The signal on line 155 may be connected to an input or port ofcontroller 250. Detection of fault signal on line 155 may causecontroller 250 to trigger ultra-fast actuator 240 to cause contacts 313and 323 (FIG. 3 ) of switch SW1 to separate from each other to form agap therebetween. In various embodiments, when the switch SW1 is“CLOSED” and the bypass power switch device 201 is in the “ON” state,for example, controller 250, although disarmed from the arc flashreduction maintenance mode, is still operational to trigger the actuator240 to cause switch SW1 to “OPEN,” in response to a fault event detectedby at least one of first fault detector 372 or a second fault detector(comparer) 375. Accordingly, when switch SW1 to “OPEN,” the current ofthe fault event is commutated to the bypass power switch device 201 sothat the fault event may be interrupted by the bypass power switchdevice 201.

The second fault detector (comparer) 375 may compare the signal receivedfrom sensor 270. The signal from sensor 270 may be representative of ahigh-current fault event. The (first fault) signal on line 275 may beconnected to a sensor input or port of controller 250. Depending on theresults of the comparison, trigger generator 370 may generate a triggersignal propagated along trigger conductor 255 to actuator 240.Specifically, the trigger signal may be communicated to ultra-fastactuator 240 to activate the actuator to cause the vacuum interrupter310 to “OPEN” such that the electrical contacts 313 and 323 are forced“OPEN” by linkage 330. In FIG. 3 , the contact 313 and 323 of switch SW1are shown as “OPEN.”

In some scenarios, the signal received by controller 250 from sensor 270may be a fault signal representative of an arc flash event. The sensor270 may send a measurement signal representative of the arc flash event.The fault signal and measurement signal may be configured to representan overcurrent or overvoltage condition due to the detected arc flashevent by the sensor 270. In some embodiments, second fault detector(comparer) 375 of controller 250 may compare the measurement signal witha threshold to detect the occurrence of the arc flash event. In eitherscenario, second fault detector (comparer) 375 may provide a controlsignal to the trigger generator 370 to cause a trigger signal to begenerated.

In some embodiments, ultra-fast actuator 240 may include a Thompson coilactuator connected to linkage 330. The actuator 240 may include apiezo-electric actuator or other ultra-fast actuators. In operation,ultra-fast actuator 240 may receive a control (trigger) signal fromcontroller 250 to cause the actuator 240 to activate. Actuator 240 whenactivated produces a fast acting force to be applied on linkage 330 thatin turn forces contacts 313 and 323 (i.e., switch SW1) in vacuuminterrupter 310 to separate.

Electro-mechanical switching device 210 when “OPEN” allows the faultcurrent of the fault event to commutate to the bypass power switchdevice 201 in the current path of the electric circuit 35 downstream.The current commutation can happen either by using a high frequencyelectronic oscillation circuit (not shown) or by an arc voltage acrossthe contact gap between contacts 313 and 323 when the contacts 313 and323 separate while carrying current. The fault event or fault current isfully commutated to the power electronic current path through bypasspower switch device 201 within tens of microseconds. The contacts 313and 323 are forced to reach the minimum contact gap to withstand atransient recovery voltage (TRV). Thus, the fault current will beinterrupted by bypass power switch device 201 and stop or eliminate thearc flash event. All this (e.g., opening the switch SW1 and interruptingthe fault current of the fault event by the bypass power switch device201) is configured to happen within about 0.5 ms or less. In otherwords, the response time is approximately 0.5 ms or less.

Bypass power switch device 201 may have a cooling device 345 configuredto perform passive cooling or active cooling. In embodiments where thecooling device 345 performs active cooling, fans may be used forcooling. For passive cooling, the cooling device 345 may include a heatsink. When fans are used, when the arc flash mitigation device 100 isarmed or when the bypass power switch device 201 is set to “ON,” theactive cooling devices are also turned “ON,” as well. Controller 250 mayprovide additional control signals to electro-mechanical switchingdevice 210 and bypass power switch device 201.

If implemented in software, the functions of controller 250 may bestored as one or more instructions or code on a computer-readable mediumand executed by a hardware-based processing unit. Computer-readablemedia corresponds to a tangible medium such as data storage media (e.g.,RAM, ROM, EEPROM, flash memory, or any other medium that can be used tostore desired program code in the form of instructions or datastructures and that can be accessed by a computer).

Instructions may be executed by one or more processors 355, such as oneor more digital signal processors (DSPs), general-purposemicroprocessors, application specific integrated circuits (ASICs), fieldprogrammable logic arrays (FPGAs), or other equivalent integrated ordiscrete logic circuitry. Accordingly, the term “processor” as usedherein may refer to any of the foregoing structure or any other physicalstructure suitable for implementation of the described techniques. Inaddition, the techniques could be fully implemented in one or morecircuits or logic elements.

Specifically, path of least resistance 107 has a first resistance.Switch SW1 has a low on-resistance. Switch SW1 has a closed positioncompleting the path to output terminal T01. A path of least resistance107 has an input (i.e., node N01) and an output (i.e., node N30) withswitch SW1 between the input (i.e., node N01) and output (i.e., nodeN30). Electro-mechanical switching device 210 has an open-circuitcondition when the switch SW1 is in an open-circuit condition position.The bi-directional bypass power switch device 201 is electricallyconnected to the path of least resistance 107 at a first locationassociated with the input (i.e., node N01) and at a second locationbetween the switch SW1 and the output (i.e., node N30).

When bi-directional bypass power switch device 201 is “ON” and switchSW1 is “OPEN,” power switch device 201 is configured to pass anelectrical current originating at node N01 or the input to node N30 orthe output. Bi-directional bypass power switch device 201 is alsoconfigured to pass an electrical current originating at node N30 or theoutput to node N01 or the input. In the scenario that a fault event isexperienced when the arc flash reduction maintenance mode is “ON,”bi-directional bypass power switch device 201 protects maintenancepersonnel by interrupting the fault current of the fault event.Alternately, any current from line L25 to node N20 may be propagatedthrough bi-directional bypass power switch device 201.

When bi-directional bypass power switch device 201 is “ON” and switchSW1 is “CLOSED,” controller 250 is configured to, in response toreceiving a signal representative of a fault event, generate a triggersignal to actuator 240 to interrupt an arc flash event or high-currentfault event by opening switch SW1 so that the fault current of the faultevent is interrupted by bypassing a portion of the path of leastresistance and channeling the fault current at node N20 tobi-directional bypass power switch device 201. Again, any current fromline L25 to node N20 may be propagated through bi-directional bypasspower switch device 201 and interrupted so that the fault event isstopped.

If the arc flash reduction maintenance mode is turned on in which switchSW1 is already “OPEN”, for example, then when the fault current reaches2× or 2.5× the rated current, the bi-directional power electronic switch201 will interrupt the fault current within 100 μs. The arc flash energyis associated with the arc flash event and may be described as the faultcurrent multiplied by the arc voltage.

The solid-state design can be packaged into the same form factor as amolded case circuit breaker (MCCB) or an air circuit breaker (ACB) sothat retrofit in existing switchgear, switchboard or panelboard, forexample, as will be discussed in relation to FIGS. 4A-4C, 6A-6B and 7 .

FIG. 4A illustrates a front perspective view of an arc flash mitigationdevice 400 with a housing with a MCCB form factor. Arc flash mitigationdevice 400 is the same as arc flash mitigation device 100 except detailsof the form factor of housing 410 will be described. Housing 410 mayinclude upper connectors 405 and lower connectors 407 for attachingcables or bus bars to conduct current from line side to load sideelectrical equipment, for example, or other electrical machine. A frontpanel or cover 402 of the housing 410 may have display panel 125,indicator 130 and control buttons 132 and 134 for easy access bypersonnel 20 (FIG. 1 ). However, it should be understood that controlpanel 120 may include other control buttons not described. FIG. 4Billustrates an end and side perspective view of the arc flash mitigationdevice 400 of FIG. 4A with a portion of the housing removed. FIG. 4Cillustrates a side view of the arc flash mitigation device 400 of FIG.4A with a portion of the housing removed. Housing 410 may locatebi-directional bypass power switch device 201 of protection electroniccircuitry 105 adjacent a back panel 412 of housing 410. Back panel 412may be mated and attached to a panel inside the switchgear 500 (FIG. 5). Electro-mechanical switching device 210 may include a vacuuminterrupter 310. The ultra-fast actuator 240 is mechanically coupled tothe vacuum interrupter 310 via a linkage 330. Electro-mechanicalswitching device 210 may have one end connected to a top end of housing410. Arc flash mitigation device 400 may include a plurality ofelectro-mechanical switching devices 210 that are arranged in parallelfor different poles. Each electro-mechanical switching device 210 isconnected to its own actuator 240 via a linkage 330.

FIG. 5 illustrates example electrical switchgear 500 to which an arcmitigation device may be installed according to some embodiments. Theswitchgear 500 may be configured to receive a standard form circuitbreaker. The switchgear 500 includes a housing 510 for housing a busbackplane assembly 520 mounted to the housing 510. The bus backplaneassembly 520 may be configured to receive a circuit breaker, which maybe electrically connected to buses of the bus backplane assembly 520 andarc flash mitigation device 100 housed in a housing with a compatibleform factor and includes control panel 120. The switchgear 500 may housethe arc flash sensor system 150.

Housing 510 may include cutouts sized to expose a front face of circuitbreakers 550 installed in the bus backplane assembly 520. The housing510 also includes the front face of circuit breakers 530, 540 and 560.Circuit breakers 530, 540 and 560 are the similar to circuit breakers550 and will be described in more detail in relation to FIG. 9 . Asillustrated, according to some embodiments, an arc mitigation device 100having a form factor substantially the same as a circuit breaker 550 maybe installed in the panelboard 500, instead of a circuit breaker. Theswitchgear 500 is shown with cutouts of various sizes to accommodateother electronic devices.

FIG. 6A illustrates a front perspective view of an arc flash mitigationdevice 600 with a housing with an air circuit breaker (ACB) form factor.Arc flash mitigation device 600 is the same, as arc flash mitigationdevice 100 except details of the form factor of housing 610 will bedescribed. A front panel or cover 602 of the housing 610 may havemounted display panel 125, indicator 130 and control buttons 132 and 134of the control panel 120 for easy access by personnel 20 (FIG. 1 ).Housing 610 may include a rear housing section 612 configured to bemated and attached to the front panel or cover 602. The rear housingsection 612 may have mounted on a rear surface rear upper connectors 605and rear lower connectors 607 for attaching housing 610 to bus barconnectors to conduct current from its line side to load side todownstream electrical equipment (FIG. 5 ), for example, or otherelectrical machine. FIG. 6B illustrates a front perspective view of thearc flash mitigation device 600 of FIG. 6A with a portion of the housingremoved. The housing 610 may locate bi-directional bypass power switchdevice 201 of protection electronic circuitry 105 adjacent front panel602 of housing 610. Electro-mechanical switching device 210 may includea vacuum interrupter 310 that is connected to a lower mounted ultra-fastactuator 240 via a linkage 330.

FIG. 7 illustrates a front perspective view of an arc flash mitigationdevice 700 with a housing with an air circuit breaker cassette formfactor. Arc flash mitigation device 700 is the same, as arc flashmitigation device 100 except details of the form factor of housing 710will be described. A front panel or cover 702 of the housing 710 mayhave mounted display panel 125, indicator 130 and control buttons 132and 134 of the control panel 120 for easy access by personnel 20 (FIG. 1). Housing 710 may include a rear housing section 712 configured to bemated and attached to the front panel or cover 702.

FIG. 9 illustrates a schematic diagram a system 900 with a hybrid arcflash mitigation system 950 (i.e., hybrid arc flash mitigation system50) used for multiple branch circuits in electric switchgear 500. Inthis scenario, the electrical circuit 25 used by maintenance personnelis replaced by a main circuit breaker 560. The arc flash reductionmaintenance mode is an arc flash reduction mode in this scenario.

The main circuit breaker 560 is coupled upstream of the node N01 and thearc flash mitigation system 100 (FIG. 2A-2B) and provides alternatingcurrent (AC). When the main circuit breaker 560 is operational and theelectro-mechanical switching device 210 is operating in the normal modeof operation (FIG. 2A), current flows in the direction of arrow 901along line L25 and to branch circuits B01 and B02, as a non-limitingexample. Alternately, when the main circuit breaker 560 is operationaland the electro-mechanical switching device 210 is operating in anopen-circuit condition (FIG. 2B), current flows in the direction ofarrows 907A, 907B and 907C, denoted in dashed lines, through the bypasspower switch device 201 to line L25. However, one or both of branchesB01 and B02 may be operational. Once the electro-mechanical switchingdevice 210 is switch to the open-circuit condition, the arc flashmitigation system 100 may transition into an arc flash mitigation modeof operation. Once the fault event is cleared, the arc flash mitigationsystem 100 may be reset to the normal mode of operation.

In operation, a high-current fault event detected by the current sensor(CS) 270 communicates a (first) fault signal on line 275 (FIG. 2A or 2B)representative of the measured amount of current to controller 250. Ahigh-current fault may be considered to be a proxy (or an indicator ofhigh risk of) for an arc flash event. If the electro-mechanicalswitching device 210 is operating in the normal mode of operation, thecontroller 250 triggers the bypass power electronic switch device 201and actuator 240 (FIG. 2B) to cause an open-circuit condition in thebypass power switch device 201 and electro-mechanical switching device210. Generally, the main circuit breaker 560 has a slower response timethan the arc flash mitigation system 100. The faster response time ofthe arc flash mitigation system 100 may help prevent an explosion fromoccurring or severe electrical equipment damage in the event of faultevents described herein.

For the sake of illustration, branch B01 includes a branch circuitbreaker 530 that is in turn electrically connected to panel 935, such asfor controlling a first set of electrical devices, such as lights, airconditioners, etc. Additionally, branch B02 includes a branch circuitbreaker 540 that is in turn electrically connected to panel 945, such asfor controlling a second set of electrical devices, such as lights, airconditioners, etc. In some embodiments, the controller 250 may alsocause one or both of the branch breakers 530 and 540 to trip in theevent of a high-current fault event sensed by current sensor 270 viacontrol signals on communication medium 951 and 952 to interrupt thehigh-current fault event. As noted previously, a high-current faultevent) corresponds to a detected or sensed current that is at least aspecified multiple (such as 2×, 2.5× or 6×) the rated current of adownstream breaker or the main breaker, or of another component of thesystem. The response time of the bypass power switch device (BPSD) 201may be between 100 μs and 0.5 milliseconds to interrupt a faultevent—faster than that of the applicable downstream branch breaker orupstream main breaker. If a fault (e.g., 915) occurs downstream of oneof the branch breakers (e.g., 530), then after the branch breaker 530that is upstream of the fault 915 opens, the branch breaker maycommunicate to the controller 250 a reset signal via communicationmedium 951. This will reclose the electro-mechanical switching device210 and permit current to flow to other branches of the circuit (such asthat associated with branch breaker 540).

In operation, controller 250 is also responsive to the arc flash sensorsystem 150. The arc detection relay 286 of the arc flash sensor system150 may have connected thereto the distributed sensors such asdistributed light or optical sensors 981 and/or at least one of currentsensors (CS) 982 along the branches. The current associated with an arcflash event may be higher than the high-current fault event. The arcdetection relay 286 may be able to determine the location of the arcflash event such as in which branch or branch segment. Each branch orbranch segment may have different sensors 981 and 982 so that the systemcan determine where the arc flash event occurred.

The plurality of distributed light or optical sensors 981 senseillumination of a flash of light representative of the arc flash eventdownstream of the path output along a plurality of circuit branches andgenerate arc sensing signals received by the arc detection relay 286.The flash sensor controller 284 is configured to process the receivedarc sensing signals, determine whether the arc flash event occurredbased on the processed arc sensing signals, and generate a fault signalto the system controller 250, in response to a determination that thearc flash event (i.e., fault event) occurred.

For example, the arc flash sensor system 150 provides a fault signal tothe controller 250 (FIG. 3 ), in response to detecting a fault eventdownstream of the arc flash mitigation device 100, such as associatedwith an arc flash event 915. The arc flash event 915 is shown occurringbetween the branch circuit breaker 530 and the panel 935. It should beunderstood, that the fault event can occur at other locations such as,without limitation, on line 25, branches B01 and B01 and between thecircuit breaker 540 and panel 945.

The arc flash mitigation system 950 may cause its electro-mechanicalswitching device 210 to trip based on sensing a fault event by at leastone of distributed optical sensors 981. The branch circuit breakers 530and 540 also may be configured to trip independent of the arc flashmitigation device 100 in response to a fault event being detected. Afterthe applicable branch circuit breakers 530 trips in response todetecting a fault event 915, the branch circuit breaker 530 may signalthe arc flash mitigation device 100 on communication medium 951. Thecommunication medium may be wired or wireless. The communication signalsmay be used to coordinate resetting and reclosing the electro-mechanicalswitching device 210, this allowing current to flow to other branches(such as circuit breaker 540).

In some scenarios, the branch circuit breaker 530 (or 540), if trippedby a sensed fault event, also transmits a notification via communicationmedium 951 (or 952) to the arc flash mitigation system 950 for displayon the control panel 120 (FIG. 3 ). In the illustration, since the faultevent 915 occurred between the branch circuit breaker 530 and the panel935, the branch circuit breaker 540 may remain powered and receivecurrent from the main circuit breaker 560 to power electrical circuitspowered by panel 945.

In various embodiments, the system 900 may include a plurality of branchcircuits downstream of the arc flash mitigation device 100, each of thebranch circuits includes an associated circuit breaker, each of thecircuit breakers is configured to open upon detection of a rated faultcurrent, and each of the circuit breakers is configured to, afteropening in response to detection of the rated fault current, send areclose signal to the system controller. The system controller 250 isfurther configured to, upon receipt of a reclose signal from a circuitbreaker: a) determine whether the arc flash event occurred downstream ofthe circuit breaker that sent the reclose signal; and b) upon confirmingthat the arc flash event occurred downstream of the circuit breaker thatsent the reclose signal, trigger the actuator that causes theelectro-mechanical switch to reclose.

In various embodiments, the system controller 250 is further configuredto, upon receipt of a reclose signal from a circuit breaker: a)determine whether the location in the system was downstream of thecircuit breaker that sent the reclose signal.

In various embodiments, the bypass power switch device 201 has a firstresponse time between 100 microseconds and 0.5 milliseconds to interruptthe arc flash event or the high-current fault event. The system mayinclude an electrical circuit, such as the main circuit breaker 560,upstream the arc flash mitigation device. The electrical circuit wouldhave a second response time slower than the first response time of thebypass power switch device 201 to any arc flash event or high-currentfault event and can be protected in the system by arc flash mitigationdevice 100 of the arc flash mitigation system 950.

FIG. 8 depicts an example of internal hardware that may be included inany of the electronic components of the system, such as controllers,sensors and computing devices. An electrical bus 800 serves as aninformation highway interconnecting the other illustrated components ofthe hardware. Processor 805 is a central processing device of thesystem, configured to perform calculations and logic operations requiredto execute programming instructions. As used in this document and in theclaims, the terms “processor” and “processing device” may refer to asingle processor or any number of processors in a set of processors thatcollectively perform a set of operations, such as a central processingunit (CPU), a remote server, or a combination of these. Read only memory(ROM), random access memory (RAM), flash memory, hard drives and otherdevices capable of storing electronic data constitute examples of memorydevices 825. A memory device 825 may include a single device or acollection of devices across which data and/or instructions are stored.Various embodiments of the invention may include a computer-readablemedium containing programming instructions that are configured to causeone or more processors, print devices and/or scanning devices to performthe functions described in the context of the previous figures.

An optional display interface 830 may permit information from bus 800 tobe displayed on a display device 835 (i.e., control panel) in visual,graphic or alphanumeric format. An audio interface and audio output(such as a speaker) also may be provided. Communication with externaldevices may occur using various communication devices 840 such as awireless antenna, a radio frequency identification (RFID) tag and/orshort-range or near-field communication transceiver, each of which mayoptionally communicatively connect with other components of the devicevia one or more communication system. Communication device(s) 840 may beconfigured to be communicatively connected to a communications network,such as the Internet, a local area network or a cellular telephone datanetwork.

The hardware may also include a user interface sensor 845 that allowsfor receipt of data from input devices 850 such as a keyboard or keypad,a joystick, a touchscreen, a touch pad, a remote control, controlbuttons, a pointing device and/or microphone. The above-disclosedfeatures and functions, as well as alternatives, may be combined intomany other different systems or applications. Various components may beimplemented in hardware or software or embedded software. Variouspresently unforeseen or unanticipated alternatives, modifications,variations or improvements may be made by those skilled in the art, eachof which is also intended to be encompassed by the disclosedembodiments.

Terminology that is relevant to the disclosure provided above includes:

The terms “memory” and “computer-readable medium” each refer to anon-transitory device on which computer-readable data, programminginstructions or both are stored. Except where specifically statedotherwise, the terms “memory” and “computer-readable medium (or media)”are intended to include single device embodiments, embodiments in whichmultiple memory devices together or collectively store a set of data orinstructions, as well as individual sectors within such devices.

The terms “processor” and “processing device” refer to a hardwarecomponent of an electronic device that is configured to executeprogramming instructions. Except where specifically stated otherwise,the singular term “processor” or “processing device” is intended toinclude both single-processing device embodiments and embodiments inwhich multiple processing devices together or collectively perform aprocess.

In this document, the term “communication line” means a wired orwireless path via which a first device sends communication signals toand/or receives communication signals from one or more other devices.Devices are “communicatively connected” if the devices are able to sendand/or receive data via a communication link. “Electronic communication”refers to the transmission of data via one or more signals between twoor more electronic devices, whether through a wired or wireless network,and whether directly or indirectly via one or more intermediary devices.

In this document, when relative terms of order such as “first” and“second” are used to modify a noun, such use is simply intended todistinguish one item from another, and is not intended to require asequential order unless specifically stated.

In addition, terms of relative position such as “vertical” and“horizontal”, or “front” and “rear”, when used, are intended to berelative to each other and need not be absolute, and only refer to onepossible position of the device associated with those terms depending onthe device's orientation. In addition, the terms “front” and “rear” arenot necessarily limited to forward-facing or rear-facing areas but alsoinclude side areas that are closer to the front than the rear, or viceversa, respectively.

1. A system comprising: an arc flash sensor configured to detect an arcflash event; and an arc flash mitigation device in communication withthe arc flash sensor, the arc flash mitigation device comprising: a pathof least resistance having a path input and a path output, the pathoutput being configured to serve as an input to a load, wherein the arcflash sensor is located downstream of the path output; an actuator; anelectro-mechanical switch between the path input and the path output; abypass power switch device that comprises a solid-state circuitinterrupter and that is configured to conduct current between the pathinput and the path output in response to an open-circuit condition ofthe switch; and a system controller configured to generate a triggersignal to activate the actuator to generate the open-circuit conditionof the electro-mechanical switch, which causes the bypass power switchdevice to interrupt a fault current associated with a fault event, inresponse to detection of the arc flash event by the arc flash sensor. 2.The system of claim 1, wherein: the arc flash sensor comprises aplurality of sensors that include at least one optical sensor and atleast one current sensor located downstream of the path output to detectthe arc flash event; and the system further comprises a plurality ofbranch circuits, each branch circuit being monitored by at least oneoptical sensor and at least one current sensor.
 3. The system of claim2, wherein: the arc flash mitigation device further comprises a currentsensor coupled upstream the path output to detect a high-current faultevent; and the system controller is also configured to generate acorresponding trigger signal to activate the actuator to generate theopen-circuit condition of the electro-mechanical switch to cause thebypass power switch device to interrupt a fault current associated withthe high-current fault event in response to detection of thehigh-current fault event by the current sensor of the arc flashmitigation device.
 4. The system of claim 1, wherein: the systemcontroller is configured to control the bypass power switch device for anormal mode of operation, an arc flash reduction mode or both; in thenormal mode of operation, the electro-mechanical switch is set in aclosed-circuit condition by the system controller; and in the arc flashreduction mode of operation, the electro-mechanical switch is set to anopen-circuit condition and the bypass power switch device is in an “ON”state.
 5. The system of claim 1, wherein the solid-state circuitinterrupter of the bypass power switch device comprises: a firsttransistor comprising an emitter; a second transistor comprising anemitter connected to the emitter of the first transistor, the firsttransistor and the second transistor form a transistor pair; and a firstvoltage-dependent resistor having a first side connected to a collectorof the first transistor and a second side connected to a collector ofthe second transistor, wherein the collector of the first transistor isconnected to the path input.
 6. The system of claim 5, wherein thesolid-state circuit interrupter further comprises: a third transistorcomprising an emitter; a fourth transistor comprising an emitterconnected to the emitter of the third transistor, the third transistorand the fourth transistor form a second transistor pair; and a secondvoltage-dependent resistor having a first side connected to a collectorof the third transistor and a second side connected to a collector ofthe fourth transistor, wherein: the collector of the third transistor isconnected to the collector of the second transistor, and the collectorof the fourth transistor is connected to the path of least resistancebetween the output terminal of the switch and the path output.
 7. Thesystem of claim 1, further comprising: a housing for housing theelectro-mechanical switch, the path of least resistance, the bypasspower switch device and the system controller, wherein the housingcomprises a molded case circuit breaker or an air circuit breaker. 8.The system of claim 1, wherein the arc flash mitigation device furthercomprises an electro-mechanical switch device that comprises theelectro-mechanical switch, and wherein: the electro-mechanical switchdevice comprises a vacuum interrupter; and the actuator comprises aThompson coil or piezo-electric actuator connected to the vacuuminterrupter.
 9. The system of claim 8, wherein the bypass power switchdevice also comprises a cooling device.
 10. The system of claim 1,wherein: the system further comprises a plurality of branch circuitsdownstream of the arc flash mitigation device; each of the branchcircuits includes an associated circuit breaker; each of the circuitbreakers is configured to open upon detection of a rated fault current;each of the circuit breakers is configured to, after opening in responseto detection of the rated fault current, send a reclose signal to thesystem controller; and the system controller is further configured to,upon receipt of a reclose signal from a circuit breaker: determinewhether the arc flash event occurred downstream of the circuit breakerthat sent the reclose signal; and upon confirming that the arc flashevent occurred downstream of the circuit breaker that sent the reclosesignal, trigger the actuator that causes the electro-mechanical switchto reclose.
 11. A method comprising: protecting, by an arc flashmitigation device, at least one electrical circuit downstream orupstream the arc flash mitigation device, the arc flash mitigationdevice including: an actuator, an electro-mechanical switch in a path ofleast resistance between a path input and a path output, the path outputbeing configured to serve as an input to a load, and a bypass powerswitch device that includes a solid-state circuit interrupter configuredto conduct current between the path input and the path output when theelectro-mechanical switch is open; detecting, by an arc flash sensor, anarc flash event downstream of the path output, wherein the arc flashsensor is in communication with the arc flash mitigation device;triggering, by the arc flash mitigation device, the actuator to open theelectro-mechanical switch in the path of least resistance in response todetection of the arc flash event by the arc flash sensor; andinterrupting a fault current representative of the detected arc flashevent by the bypass power switch device of the arc flash mitigationdevice.
 12. The method of claim 11, wherein: the arc flash mitigationdevice comprises a current sensor connected upstream of the path output;and the protecting, by the arc flash mitigation device, furthercomprises: detecting, by the current sensor a high-current fault eventdownstream of the path output, triggering, by the arc flash mitigationdevice, the actuator to open the electro-mechanical switch in the pathof least resistance in response to detection of the high-current eventby the current sensor of the arc flash mitigation device, andinterrupting a fault current representative of the high-current faultevent by the bypass power switch device of the arc flash mitigationdevice.
 13. The method of claim 11, wherein: the at least one electricalcircuit is downstream and each electrical circuit includes a branchcircuit with a circuit breaker; and the detecting, by the arc flashsensor, comprises detecting an occurrence of the arc flash event in anyof the branch circuits.
 14. The method of claim 11, wherein the arcflash sensor comprises a plurality of optical sensors, each of which isassociated with a branch circuit to sense an occurrence of illuminationrepresentative of the detected arc flash event at the associated branchcircuit.
 15. The method of claim 14, wherein the arc flash sensorcomprises a plurality of current sensors, each of which is associatedwith a branch circuit to sense an occurrence of the fault currentrepresentative of the detected arc flash event at the current sensor'scorresponding branch circuit.
 16. The method of claim 11, wherein thesolid-state circuit interrupter of the bypass power switch devicecomprises: a first transistor comprising an emitter; a second transistorcomprising an emitter connected to the emitter of the first transistor;and a first voltage-dependent resistor having a first side connected toa collector of the first transistor and a second side connected to acollector of the second transistor, wherein the first transistor and thesecond transistor form a first transistor pair, and wherein thecollector of the first transistor is connected to the path input. 17.The method of claim 16, wherein the solid-state circuit interrupter ofthe bypass power switch device further comprises: a third transistorcomprising an emitter; a fourth transistor comprising an emitterconnected to the emitter of the third transistor; and a secondvoltage-dependent resistor having a first side connected to a collectorof the third transistor and a second side connected to a collector ofthe fourth transistor, wherein the third transistor and fourthtransistor form a second transistor pair, wherein the collector of thethird transistor is connected to the collector of the second transistor,and wherein the collector of the fourth transistor is connected to thepath of least resistance between the output terminal of the switch andthe path output.
 18. The method of claim 11, wherein: the arc flashmitigation device further comprises an electro-mechanical switch devicethat comprises the electro-mechanical switch; the electro-mechanicalswitch comprises a vacuum interrupter with a vacuum chamber; and theactuator comprises a Thompson coil or piezo-electric actuator connectedto the vacuum interrupter.
 19. The method of claim 18, wherein: thebypass power switch device comprises a cooling device; and the methodfurther comprises cooling the bypass power switch device by the coolingdevice.
 20. The method of claim 11, wherein the bypass power switchdevice has a response time between 100 microseconds and 0.5 millisecondsto interrupt the arc flash event.